counter 3 bits with Reset asynchrone

// Design Name : counter 3 bits
   // File Name   : counter 3 bits.v
  // Function    : description low level of counter 3 bits with Reset asynchrone
  // Coder       : BOURAOUI KACEM
// Bascule D
module BASCULE(d,clk,q);
input d,clk;
output reg q;
always @(posedge clk)
q <= d;
endmodule
// module counter
module counter(clk,rst,Q1,Q2,Q3);
input clk,rst;
inout Q1,Q2,Q3;
wire i,j,k,D1,D2,D3;
and and1(D1,~Q1,~rst);
//instantiation of bascule D
BASCULE bascule1(D1,clk,Q1);
xor xor1(i,Q1,Q2);
and and2(D2,i,~rst);
and and3(j,Q1,Q2);
xor xor2(k,j,Q3);
and and4(D3,k,~rst);
BASCULE bascule2(D2,clk,Q2);
BASCULE bascule3(D3,clk,Q3);
endmodule
//  counter's testbench
// we define here the 
`timescale 1ns/1ns 
module testchip;
// always we define the out put as a wire and the input as a regiter 
reg d1;
wire Q1,Q2,Q3;
counter counter1(clk,d1,Q1,Q2,Q3);
  initial
// Initialize all variables
	begin
	clk=1'b1; d1=0; 
	#5;
	//a=1; b=1'b1;c=1;rst=1;
        #10;
        //a=1;b=1'b1;c=0; rst=1;
        #15;
        //a=1'b1;b=1;c=0;rst=0;
        #5 $finish;
end
 //Clock generator
always 
	begin
	#5 clk=~clk;
	end
// load the file 
initial 
begin 
$dumpfile("counter.vcd");
$dumpvars;
end
// display of the results 
initial
begin
        $display("time,\t\tclk\ta\tQ1\tQ2\tQ3");
//it is  sensitive to the variation of clk,d1,Q1,Q2,Q3 
	$monitor("%g\t \t%b\t%b\t%b\t%b\t%b", $time,clk,d1,Q1,Q2,Q3);
end
endmodule