4 Bit Ripple Carry Adder
Submitted by abettino on Tue, 03/02/2010 - 21:55
This snippet demonstrates a straight forward approach to implementing a 4 bit Ripple Carry Adder in Verilog. Also check out the parameterized approach which scales very well.
Basic full adder.
module full_adder ( input a, input b, input cin, output sum, output cout ); assign sum = a ^ b ^ cin; assign cout = (a & b) | ((a^b) & cin); endmodule
4 bit ripple carry adder.
// Ripple carry adder. module rca ( input [3:0] A, input [3:0] B, output [4:0] sum ); wire [4:0] carry_out; full_adder fa0(.a(A[0]),.b(B[0]),.cin(1'b0), .cout(carry_out[1]),.sum(sum[0])); full_adder fa1(.a(A[1]),.b(B[1]),.cin(carry_out[1]), .cout(carry_out[2]),.sum(sum[1])); full_adder fa2(.a(A[2]),.b(B[2]),.cin(carry_out[2]), .cout(carry_out[3]),.sum(sum[2])); full_adder fa3(.a(A[3]),.b(B[3]),.cin(carry_out[3]), .cout(carry_out[4]),.sum(sum[3])); // assign the final sum bit. assign sum[4] = carry_out[4]; endmodule

How can I run this in
How can I run this in Terminal using iverilog -t command?
I am not too familiar with
I am not too familiar with Icarus verilog, but I know that you will need to create a test bench in order to stimulate the module. You can then look at output with the simulator.