Accumulator (under 10)

module accumulator(
		input 	wire 		rst_n
	, 	input 	wire 		clk
	,	input	wire		 start
	,	input	wire  [3:0]	 din			//input <= 10
	,	output	reg   [9:0]	 dout
	,	output	reg		 dout_vld
	);
 
reg [7:0]	k;
 
always @(posedge clk or negedge rst_n or posedge start)
begin
	if(~rst_n)
	begin
		dout 	<= 	10'b0;
		dout_vld	<= 	1'b0;
		k		<=	8'b0;
	end
	else if(start)
	begin
		dout		<= 	10'b0;
		dout_vld	<=	1'b0;
		k		<=	8'b0;
	end
	else if(k < 8'd99 )
	begin
		dout		<= din + dout;
		k		<= k + 8'b1;
	end
	else if(k == 8'd99)
	begin
		dout_vld	<= 1'b1;
		k		<= k + 8'b1;
	end
end
 
endmodule