Barrel_Shifter

module barrel_shifter(
		input 	wire 			rst_n
	,	input 	wire 			clk
	, 	input 	wire 			data_in_vld
	, 	input 	wire 			left_or_right
	, 	input 	wire 	[3:0]	        num_bits
	, 	input 	wire	[7:0]	        data_in
	,	output	reg			data_out_vld
	,	output 	reg	[7:0]	        data_out
);
 
parameter		left	=	1'b0;
parameter		right	= 	1'b1;
 
 
 
always @(posedge clk or negedge rst_n) 
begin
	if(~rst_n)
	begin
		data_out 			<= 8'b0;
		data_out_vld		<= 1'b0;
	end
	else if(data_in_vld)
	begin
		data_out_vld	<=	1'b0;
		if(left_or_right == right)
			casex(num_bits)
  		  		3'd0    : begin data_out <=       data_in      ;	data_out_vld <= 1'b1; end
  		  		3'd1    : begin data_out <= {1'b0,data_in[7:1]};	data_out_vld <= 1'b1; end
  		  		3'd2    : begin data_out <= {2'b0,data_in[7:2]};	data_out_vld <= 1'b1; end
  		  		3'd3    : begin data_out <= {3'b0,data_in[7:3]};	data_out_vld <= 1'b1; end
  		  		3'd4    : begin data_out <= {4'b0,data_in[7:4]};	data_out_vld <= 1'b1; end
  		  		3'd5    : begin data_out <= {5'b0,data_in[7:5]};	data_out_vld <= 1'b1; end
  		  		3'd6    : begin data_out <= {6'b0,data_in[7:6]};	data_out_vld <= 1'b1; end
  		  		3'd7    : begin data_out <= {7'b0,data_in[7  ]};	data_out_vld <= 1'b1; end
  			endcase
		else if(left_or_right == left)
			casex(num_bits)
  		  		3'd0    : begin data_out <=  data_in           ;   	data_out_vld <= 1'b1; end
  		  		3'd1    : begin data_out <= {data_in[6:0],1'b0};	data_out_vld <= 1'b1; end
  		  		3'd2    : begin data_out <= {data_in[5:0],2'b0};	data_out_vld <= 1'b1; end
  		  		3'd3    : begin data_out <= {data_in[4:0],3'b0};	data_out_vld <= 1'b1; end
  		  		3'd4    : begin data_out <= {data_in[3:0],4'b0};	data_out_vld <= 1'b1; end
  		  		3'd5    : begin data_out <= {data_in[2:0],5'b0};	data_out_vld <= 1'b1; end
  		  		3'd6    : begin data_out <= {data_in[1:0],6'b0};	data_out_vld <= 1'b1; end
  		  		3'd7    : begin data_out <= {data_in[  0],7'b0};	data_out_vld <= 1'b1; end
  			endcase
	end
end
 
endmodule