CARRY SAVE ADDER

module carry_save_adder(
		input	wire		rst_n
	,	input	wire		clk
	,	input	wire		w_in
	,	input	wire		p_in
	,	input	wire	[7:0]	sum_p
	,	input	wire	[7:0]	carry_p
	,	input	wire	[3:0]	din
	,	output	reg	[7:0]	sum
	,	output	reg	[7:0]	carry
	);
 
always @(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		sum	<=		8'b0;
		carry	<=		8'b0;
	end
	else if(p_in)
	begin
		sum	<=		sum_p;
		carry	<=		carry_p;
	end
	else if(w_in)
	begin
		sum	<=		sum ^ {4'b0, din} ^ {carry, 1'b0};
		carry	<=		sum & {4'b0, din} | {4'b0, din} & {carry, 1'b0} | {carry, 1'b0} & sum;
	end
end
 
endmodule