CARRY LOOKAHEAD ADDER

module carry_lookahead_adder(
		input 	wire 		rst_n
	,	input	wire		clk
	,	input	wire		hrst
	,	input	wire		w_in
	,	input	wire		p_in
	,	input	wire	[5:0]	sum_p
	,	input	wire	[3:0]	din
	,	output	reg	[5:0]	sum
	);
 
wire	[5:0]	din_t;	
wire	[5:0]	g;
wire	[5:0]	p;
wire	[5:1]	ci;
 
assign din_t	=	{2'b0,din};
assign g		=	{	sum[5] & din_t[5], 
					sum[4] & din_t[4], 	
					sum[3] & din_t[3], 
					sum[2] & din_t[2],
					sum[1] & din_t[1],
					sum[0] & din_t[0]
					};
 
assign p		=	{	sum[5] | din_t[5],
					sum[4] | din_t[4],
					sum[3] | din_t[3],
					sum[2] | din_t[2],
					sum[1] | din_t[1],
					sum[0] | din_t[0]
					};
 
assign			ci[5]	=	g[4] | (p[4] & ci[4]);
assign			ci[4]	=	g[3] | (p[3] & ci[3]);
assign			ci[3]	=	g[2] | (p[2] & ci[2]);
assign			ci[2]	=	g[1] | (p[1] & ci[1]);
assign			ci[1]	=	g[0];
 
always @(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		sum		<=		6'b0;
	end
	else if(hrst)
	begin
		sum		<=		6'b0;
	end
	else if(p_in)
	begin
		sum		<=		sum_p;
	end
	else if(w_in)
	begin
		sum[0]	<=		sum[0] ^ din_t[0]		 ;
		sum[1]	<=		sum[1] ^ din_t[1] ^ ci[1];
		sum[2]	<=		sum[2] ^ din_t[2] ^ ci[2];
		sum[3]	<=		sum[3] ^ din_t[3] ^ ci[3];
		sum[4]	<=		sum[4] ^ din_t[4] ^ ci[4];
		sum[5]	<=							ci[5];
	end
end
 
endmodule