BIT MULTIPLIER(8 BITS input)

module bit_multiplier(
		input	wire			rst_n
	,	input	wire			clk
	,	input	wire			din_vld
	,	input	wire	[7:0]	        multiplicand
	,	input	wire	[7:0]	        multiplier
	,	output	reg	[15:0]	product
	,	output	reg			dout_vld
	);
 
reg		[3:0]	        counter;
reg		[7:0]	        reg_cand;
reg		[7:0]	        reg_er;
reg		[15:0]	reg_product;
 
reg				din_vld1;
reg				din_vld2;
 
reg				m_enable;
 
wire  [15:0]  reg_product_l = ~(counter > 0 & counter < 9) ? 16'b0 : reg_er[counter - 1] 
																	? (reg_product[15:0] + {reg_cand, 8'b0}) : reg_product;
////////////////////////////////////////////////////////////////////////////////	//din_vld
always @(posedge clk or negedge rst_n)											
begin
	if(~rst_n)
	begin
		din_vld1	<=	1'b0;
		din_vld2	<=	1'b0;
	end
	else if(~m_enable)
	begin
		din_vld1	<=	din_vld;
		din_vld2	<=	din_vld1;
	end
	else if(m_enable)
	begin
		din_vld1	<=	1'b0;
		din_vld2	<=	1'b0;
	end
end
////////////////////////////////////////////////////////////////////////////////	//m_enable
always @(posedge clk or negedge rst_n)										
begin
	if(~rst_n)
	begin
		m_enable	<=	1'b0;
	end
	else if(din_vld1 & ~din_vld2)
	begin
		m_enable	<=	1'b1;
	end
	else if(counter == 4'd9)
	begin
		m_enable	<=	1'b0;
	end
end
////////////////////////////////////////////////////////////////////////////////	//counter
always @(posedge clk or negedge rst_n)											
begin
	if(~rst_n)
	begin
		counter		<=	4'b0;
	end
	else if(~m_enable)
	begin
		counter		<=	4'b0;
	end
	else if(m_enable)
	begin
		counter		<=	counter + 1'b1;
	end
end
////////////////////////////////////////////////////////////////////////////////	//dout_vld
always @(posedge clk or negedge rst_n)											
begin
	if(~rst_n)
	begin
		dout_vld	<=	1'b0;
	end
	else if(~m_enable)
	begin
		dout_vld	<=	1'b0;
	end
	else if(counter ==  4'd9)
	begin
		dout_vld	<=	1'b1;
	end
end
////////////////////////////////////////////////////////////////////////////////	//reg
always @(posedge clk or negedge rst_n)											
begin
	if(~rst_n)
	begin
		reg_cand	<=	8'b0;
		reg_er	<=	8'b0;
	end
	else if(din_vld1 & ~din_vld2)
	begin
		reg_cand	<=	multiplicand;
		reg_er	<=	multiplier;
	end
	else if(~m_enable)
	begin
		reg_cand	<=	8'b0;
		reg_er	<=	8'b0;
	end
end
////////////////////////////////////////////////////////////////////////////////	//multiply
always @(posedge clk or negedge rst_n)											
begin
	if(~rst_n)                         reg_product			<=		16'b0;
	else if(~m_enable)	      reg_product			<=		16'b0;
	else if(m_enable & counter<4'd10)  reg_product      	<= 		roduct_l;
end
////////////////////////////////////////////////////////////////////////////////
always @(negedge clk)
begin
	if(m_enable & counter < 4'd10)		reg_product[15:0]	<=		{1'b0, reg_product[15:1]};
end
////////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
begin
	if(~rst_n)
	begin
		product			<=		16'b0;
	end
	else if(~m_enable)
	begin
		product			<=		16'b0;
	end
	else if(counter == 4'd9)
	begin
		product			<=		reg_product;
	end
end
////////////////////////////////////////////////////////////////////////////////
endmodule