// Basic full adder module.
module full_adder
(
  input  a,
  input  b,
  input  cin,
  output sum,
  output cout
);

assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a^b) & cin);

endmodule


// Parameterized Ripple carry adder.
module rca #(parameter N=4)
(
 input [N-1:0] A,
 input [N-1:0] B,
 output [N:0]  sum
 );

// generate variable.
genvar         ii;

wire [N:0]       carry_out;

// assing the first carry in bit to 0.
assign carry_out[0] = 1'b0;

// generate statement connect all the wires.
generate for (ii=0;ii<N;ii=ii+1) 
begin : RCA_GEN
  full_adder full_adder
    (
     .a(A[ii]),
     .b(B[ii]),
     .cin(carry_out[ii]),
     .cout(carry_out[ii+1]),
     .sum(sum[ii])
     );
end
endgenerate

// assign the final sum bit.
assign sum[N] = carry_out[N];

endmodule
  
`define TEST_N 8
module tb_rca;

integer A;
integer B;
wire [`TEST_N:0] sum;

integer    error_cnt;

rca #(.N(`TEST_N)) dut
(
 .A(A),
 .B(B),
 .sum(sum)
 );

initial begin
  error_cnt = 0;
  for(A=0;A<(1'b1<<`TEST_N);A=A+1) begin
    for(B=0;B<(1'b1<<`TEST_N);B=B+1) begin
      #10 $display("A=%d B=%d sum=%d",A,B,sum);
      if (sum != A+B ) error_cnt = error_cnt + 1;
    end
  end
  $display("simulation done with %d errors",error_cnt);
  
  $stop;

end

endmodule