SystemVerilog always_comb

The always_comb block in SystemVerilog provides a means to prevent simulation and synthesis mismatches. The idea is that both the simulator and synthesizer will be able to analyze this block and determine if it properly infers combinational logic. If it does not, an error can be thrown. This snippet demonstrates the most basic usage of this type of block and it also demonstrates the usage of the unique keyword. This keyword ensure that only one branch of the case statement is active at any time.

module systemverilog_always_comb
(
  input  logic [3:0] data_input,
  input  logic [1:0] sel,
  output logic       data_output
);
 
always_comb 
  begin : sysverilog_always_comb   // optional label.
    unique case (sel)
      2'b00 : data_output = data_input[0];
      2'b01 : data_output = data_input[1];
      2'b10 : data_output = data_input[2];
      2'b11 : data_output = data_input[3];
    endcase
  end   : sysverilog_always_comb   // optional label.
 
endmodule