SystemVerilog always_ff

The always_ff block in SystemVerilog provides a means to prevent simulation and synthesis mismatches. The idea is that both the simulator and synthesizer will be able to analyze this block and determine if it properly infers sequential logic. If it does not, an error can be thrown. This snippet demonstrates the most basic usage of this type of block.

module systemverilog_always_ff 
(
  input  logic clk,
  input  logic d,
  output logic q
);
 
always_ff @(posedge clk)         // always_ff
  begin : sysverilog_always_ff   // optional label.
    q <= d;
  end   : sysverilog_always_ff   // optional label.
 
endmodule