Skip navigation.
Home
hdlsnippets
Verilog Snippets | VHDL Snippets | SystemVerilog Snippets | About | Links
Home

SystemVerilog Array Initilization

Submitted by abettino on Thu, 03/25/2010 - 15:03

Array initialization in SystemVerilog has a syntax very similar to array initialization in C. The main difference is the usage of the quote (') character at the beginning of each row element of the array.

module systemverilog_initialize_array;
 
int test_array[10] = '{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA};
int ii,jj;
int test_array_2d[3][10] = '{'{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA},
                             '{'h81,'h82,'h83,'h84,'h85,'h86,'h87,'h88,'h89,'h8A},
                             '{'h101,'h102,'h103,'h104,'h105,'h106,'h107,'h108,'h109,'h10A}};
initial begin
  for (ii=0;ii<10;ii++) begin
    $display("test_array[%d] = %d",ii,test_array[ii]);
  end
 
  for(jj=0;jj<3;jj++) begin
    for(ii=0;ii<10;ii++) begin
      $write("%03x ", test_array_2d[jj][ii]);
    end
    $write("\n");
  end
 
  $stop;
end
 
endmodule

»