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SystemVerilog foreach

Submitted by abettino on Thu, 03/25/2010 - 15:10

The foreach construct in SystemVerilog provides a compact way of indexing through an array. The snippet below demonstrates the syntax of how to use foreach to go through both a 1 dimensional array and a 2 dimensional array.

module systemverilog_initialize_array_foreach;
 
int test_array[10] = '{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA};
int test_array_2d[3][10] = '{'{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA},
                             '{'h81,'h82,'h83,'h84,'h85,'h86,'h87,'h88,'h89,'h8A},
                             '{'h101,'h102,'h103,'h104,'h105,'h106,'h107,'h108,'h109,'h10A}};
initial begin
  foreach(test_array[ii]) begin
    $display("test_array[%d] = %d",ii,test_array[ii]);
  end
 
  foreach(test_array_2d[jj,ii]) begin
    $write("%03x ", test_array_2d[jj][ii]);
    if (ii==9) $write("\n");
  end
  $stop;
end
 
endmodule

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