SystemVerilog Multiplexor
Submitted by abettino on Sun, 03/21/2010 - 09:36
A multiplexor written in SystemVerilog can take advantage of a few of SystemVerilog's keywords. For instance, the always_comb block is used to indicate combinational logic and the unique case statement makes it clear to the sythesizer and simulator that only one branch in the case statement should ever be taken. Also check out the Verilog implementation of the multiplexor.
module mux4_2 ( input logic a,b,c,d, input logic [1:0] sel, output logic z ); always_comb begin unique case (sel) 2'b00 : z = a; 2'b01 : z = b; 2'b10 : z = c; 2'b11 : z = d; endcase end endmodule module mux4_2_incomplete ( input logic a,b,c, input logic [1:0] sel, output logic z ); always_comb begin unique case (sel) 2'b00 : z = a; 2'b01 : z = b; 2'b10 : z = c; default : z = 'x; endcase end
| Attachment | Size |
|---|---|
| mux4_2.sv | 528 bytes |