Parameterized Priority Selector
Submitted by abettino on Wed, 02/03/2010 - 18:43
A parameterized priority selector can be written much more concisely than if each input encoding was explicitly coded. Also notice that with the SystemVerilog parameter syntax, we can use the parameter in the port list before it is actually declared.
module parameterized_priority ( input logic [NUM_INPUTS-1:0] input_data, input logic [NUM_INPUTS-1:0] select, output logic output_data ); parameter NUM_INPUTS=5; int ii; always_comb begin output_data = 'x; for(ii=0;ii<NUM_INPUTS;ii++) if (select[ii]) output_data = input_data[ii]; end endmodule
This code was synthesized with the Altera synthesizer with the expected results.
| Attachment | Size |
|---|---|
| priority_parameterized.PNG | 5.6 KB |
| parameterized_priority.sv | 369 bytes |
