SystemVerilog Task

module tbTasks;
 
bit clk;                       // clock signal.
logic [7:0] data_mem [0:255];  // array to simulate a memory.
int         ii,error_cnt;      // test variables.
 
logic [7:0] data_read;         // store data read back from memory.
 
initial begin
  forever #10 clk = ~clk;      // generate a clock.
end
 
initial begin
  error_cnt = 0;
  for(ii=0;ii<256;ii++) begin  // Write the memory.
    WriteMem(ii,ii);
  end
  for(ii=0;ii<256;ii++) begin  // Read back the memory and check the data.
    ReadMem(ii,data_read);
    if (data_read !== ii) begin 
      $display("Data error at ii=%d value=%d",ii,data_read);
      error_cnt++;
    end
  end
  $display("Simulation done with %d errors",error_cnt);
  $stop;
end
 
// The read memory task.
task ReadMem(input logic [7:0] addr, output logic [7:0] data);
  data = data_mem[addr];
endtask
 
// The write memory task.
task WriteMem(input logic [7:0] addr, input logic [7:0] data);
  data_mem[addr] = data;
  @(posedge clk);
endtask
 
endmodule