SystemVerilog Time

SystemVerilog includes many improvements that remove the ambiguity with timescales found in Verilog. Instead of the `timescale operations, the timescale can be defined at the module level with the timeunit and timeprecision directives. Also useful is the ability to specify units when using the #(delay) syntax. The following snippet shows how these features may be used.

module system_verilog_time;
  timeunit 1ns;
  timeprecision 1ps;
 
initial begin
  #10ns    $display("%f", $realtime);
  #17ps    $display("%f", $realtime);
  #0.100ns $display("%f", $realtime);
end
 
endmodule