Verilog Accumulator
Submitted by abettino on Wed, 03/31/2010 - 15:00
An accumulator can be used to keep a running tally of a value over time. This snippets demonstrates a simple accumulator in Verilog with a synchronous clear signal.
module accum #(parameter WIDTH=8) ( input clk, clear, input [WIDTH-1:0] d, output reg [WIDTH-1:0] q ); always @(posedge clk) if (clear) q <= 0; else q <= q + d; endmodule