Verilog And and Verilog And

Verilog has two different and operators. There is a bitwise and and a logical and. Using these operators in the wrong situations can cause undesired behavior. The bitwise verilog and operator will provide a bit vector that results from applying a bitwise and to each element in the source vectors. The logical verilog and operator will return 1 if both of the arguments are non zero. The following snippets demonstrates this behavior.

module verilog_and;
  reg [3:0] verilog_and_1;
  reg [3:0] verilog_and_2;
  reg [3:0] verilog_and_result;
  initial begin
    verilog_and_1 = 4'hc;
    verilog_and_2 = 4'hf;
    verilog_and_result=verilog_and_1 & verilog_and_2;
    $display("bitwise and = %x", verilog_and_result);
    verilog_and_result = verilog_and_1 && verilog_and_2;
    $display("logic and = %x", verilog_and_result);
    $stop;
  end
endmodule