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Verilog Concatenation

Submitted by abettino on Sun, 03/21/2010 - 12:35

Concatenation is a useful feature in Verilog. It allows multiple signals to be combined into one signal. Concatenation in Verilog is achieved by using the curly braces with the signals to be concatenated separated by commas inside as demonstrated in the following snippet.

module verilog_concat;
 
reg [7:0] register_a;
reg [3:0] register_b;
reg [3:0] register_c;
reg [2:0] register_d;
 
initial begin
  register_b = 4'hA;
  register_c = 4'hF;
  register_d = 3'h7;
 
  // concat register b and register c into register a
  register_a = {register_b,register_c};
  $display("register a=%x",register_a);
 
  // concat register c and register b into register a
  register_a = {register_c,register_b};
  $display("register a=%x",register_a);
 
  //concat register d, 1'b0, and register b into register a.
  register_a = {register_d,1'b0,register_b};
  $display("register a=%x",register_a);
 
  $stop;
 
end
 
endmodule

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