Counter with clear and enable
Submitted by abettino on Sun, 02/28/2010 - 21:20
This is a simple Verilog counter with clear and enable signals. The width of the counter is configurable with the parameter.
module counter_clear #(parameter WIDTH=8) ( input clk, input clear, input enable, output reg [WIDTH-1:0] count ); always @(posedge clk) if (clear) count <= 0; else if (enable) count <= count + 1; endmodule
| Attachment | Size |
|---|---|
| counter_clear.v | 276 bytes |