Verilog CRC CRC16CCITT
Submitted by abettino on Wed, 03/31/2010 - 13:39
The CRC 16 CCITT is a common CRC implementation. This CRC algorithm is realized with a simple linear feeback shift register with exclusive taps inserted in 4 different stages in the CRC. A serial bitstream is shifted in and the 16 bit output CRC is valid at any time.
module crc16ccitt ( input clk, enable, reset_crc, data, output reg [15:0] crc ); wire xor12,xor5,xor0,xor16; assign {xor16,xor0,xor5,xor12} = {crc[15]^data,xor16^1'b0,xor16^crc[4],xor16^crc[11]}; always @(posedge clk) if (reset_crc) crc <= 16'hFFFF; else if (enable) crc <= {crc[14:12],xor12,crc[10:5],xor5,crc[3:0],xor0}; endmodule
What username are you trying
What username are you trying to activate? Please email admin@hdlsnippets.com if you continue to have problems.
Problem with activation
Hi there, I dont know if I am writing in a proper board but I have got a problem with activation, link i receive in email is not working...