Verilog Dual Edge Detector

It is often necessary to detect when a particular signal is transitioning from high to low or low to high. It is also sometimes useful to get a pulse that is a single clock cycle wide to trigger other logic in the system. This snippet demonstrates how a single cycle wide pulse can be generated on the falling edge of a signal or the rising edge of a signal.

module dual_edge_detect
(
 input  clk,
 input  signal,
 output pulse
);
 
reg     signal_prev;
 
always @(posedge clk) signal_prev <= signal;
 
assign pulse = (~signal & signal_prev) | (signal & ~signal_prev);
 
endmodule