Verilog Flip Flops
Submitted by abettino on Tue, 02/02/2010 - 08:17
Here are a few examples of flip flops. From these examples, one should be able to build any variation of the desired asynchronous set, resets and clears. These snippets use the Verilog 2001 style port listing.
Rising edge flip flop.
module rising_edge_ff ( input clk, // clock signal. input d, // data input. output reg q // data output ); always @(posedge clk) begin q <= d; end endmodule
Falling edge flip flop.
module falling_edge_ff ( input clk, // clock signal. input d, // data input. output reg q // data output ); always @(negedge clk) begin q <= d; end endmodule
Rising edge flip flop with rising edge asynchronous reset.
module ff_async_rising_reset ( input clk, // clock signal. input reset, // asynchronous reset. input d, // data input. output reg q // data output ); always @(posedge clk or posedge reset) begin if (reset) q <= 1'b0; else q <= d; end endmodule
Rising edge flip flop with synchronous set.
module ff_sync_set ( input clk, // clock signal. input set, // synchronous set. input d, // data input. output reg q // data output ); always @(posedge clk) begin if (set) q <= 1'b1; else q <= d; end endmodule
Rising edge flip flop with asynchronous negative edge reset and clock enable.
module ff_async_reset_ce ( input clk, // clock signal. input n_reset, // asynchronous reset. input ce, // clock enable. input d, // data input. output reg q // data output ); always @(posedge clk or negedge n_reset) begin if (!n_reset) q <= 1'b0; else if (ce) q <= d; end endmodule
| Attachment | Size |
|---|---|
| flip_flops.v | 1.47 KB |