Verilog ifdef
Submitted by abettino on Wed, 03/10/2010 - 20:40
Verilog supports a limited number of compiler directive statements. One particular useful statement is the Verilog `ifdef. The syntax for the `ifdef is "`ifdef NAME". The ifdef should be paired with the `define directive which has the syntax "`define NAME VALUE". The `ifdef can be used in conjunction with the `else and must be closed with the `endif. Both of these directives are very similar to the C equivalent. The following example shows how a particular module may be conditionally instantiated.
`define USE_MODULE_A module verilog_if_def_example ( input clk, input din, output reg dout ); // instantiate either Module A or B // depending on the `ifdef `ifdef USE_MODULE_A module_a module_inst ( .clk (clk), .din (din), .dout(dout) ); `else module_b module_inst ( .clk (clk), .din (din), .dout(dout) ); `endif endmodule // simple positive edge flip flop module module_a ( input clk, input din, output reg dout ); always @(posedge clk) dout <= din; endmodule // simple negative edge flip flop module module_b ( input clk, input din, output reg dout ); always @(negedge clk) dout <= din; endmodule
| Attachment | Size |
|---|---|
| verilog_if_def_example.v | 685 bytes |
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