Verilog Inferred RAM

Submitted by abettino on Mon, 03/22/2010 - 16:32

When doing an FPGA design, it is sometimes useful to write some HDL code to infer a block RAM element. Most synthesizers will support this construct. The following snippet demonstrates how to infer a block ram in Verilog.

module verilog_ram_infr #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256)
(
 input                   clk,       // clock signal.
 input  [ADDR_WIDTH-1:0] addr,      // address signal.
 input                   we,        // write enable signal.
 input  [DATA_WIDTH-1:0] data_in,   // data input.
 output [DATA_WIDTH-1:0] data_out   // data output.
);
 
reg [DATA_WIDTH-1:0]     mem [0:DEPTH-1]; // memory array.
 
always @(posedge clk)
  if (we) mem[addr] <= data_in;       // latch data on we.
 
assign data_out = mem[addr];          // data output.
 
endmodule

Attachment	Size
verilog_ram_infr.v	1.22 KB

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Verilog Inferred RAM

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