Multiplexer
Submitted by abettino on Wed, 02/24/2010 - 20:04
Multiplexers are easy to code in Verilog. Make sure that when describing combinational logic such as this to complete the case statements. If this is not done, unintentional latches may be inferred. Also notice the wildcard in the sensitivity list. This can be a very useful shortcut.
module mux4_2 ( input a, input b, input c, input d, input [1:0] sel, output reg z ); always @* begin case (sel) 2'b00 : z = a; 2'b01 : z = b; 2'b10 : z = c; 2'b11 : z = d; endcase end endmodule
And here is a version with an incomplete case statement.
module mux4_2_incomplete ( input a, input b, input c, input [1:0] sel, output reg z ); always @* begin case (sel) 2'b00 : z = a; 2'b01 : z = b; 2'b10 : z = c; default : z = 1'bx; endcase end endmodule
| Attachment | Size |
|---|---|
| mux4_2.v | 554 bytes |