Odd Clock Divider
Submitted by abettino on Fri, 02/26/2010 - 08:02
There may be many situations where it is desired to divide an input clock by an odd value. This verilog module demonstrates how and odd clock divider can be constructed for divide values of 3,5,7 or 9. It can be expanded to support other divide factors as well.
// Odd clock divider. Supported input div_factors // are 3,5,7, and 9. module odd_divide ( input clk, // clock to divide. input reset, // reset. input [3:0] div_factor, // 3,5,7 or 9 output clk_div // divided clock ); reg clk_neg,clk_pos; reg [3:0] div_counter; wire [3:0] thresh = div_factor - 1; // Divide counter. always @(posedge clk or posedge reset) if (reset) div_counter <= 0; else if (div_counter==thresh) div_counter <= 0; else div_counter <= div_counter+1; // Clock neg logic. always @(negedge clk) begin case (div_factor) 4'h3 : clk_neg <= div_counter[1]; 4'h5 : clk_neg <= div_counter[1]; 4'h7 : clk_neg <= div_counter[2]; 4'h9 : clk_neg <= div_counter[2]; default : clk_neg <= div_counter[1]; endcase end // Clock pos logic. always @* begin case (div_factor) 4'h3 : clk_pos = div_counter[1]; 4'h5 : clk_pos = div_counter[1]; 4'h7 : clk_pos = div_counter[2]; 4'h9 : clk_pos = div_counter[2]; default : clk_pos = div_counter[1]; endcase end // output clock. assign clk_div = clk_pos | clk_neg; endmodule
| Attachment | Size |
|---|---|
| odd_divide.v | 1.17 KB |
Not really for FPGAs
This is a common mistake from basic college classes. If you look up most FPGA texts, including several docs from Xilinx, you'll see this form is discouraged. Mainly because it over-abstracts clocking, and might not make good use of the dedicated BUFG routing on the FPGA.
for clocks that are sent off chip, you can also use oversampling modules, like the ODDR or OSERDES to get close to the correct duty ratio.
I suggest looking into using the DCMs/PLLs in the FPGA as well.
Good point
This is a very important point. An understanding of the FPGAs clocking structure is necessary before attempting to generate clocks in the FPGA. Generally speaking whenever you need to generate a clock in FPGA, it is best to use the DCM or PLL.