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Parameterized Priority Encoder

This snippet demonstrates a Verilog implementation of a parameterized priority encoder. Also see the SystemVerilog parameterized priority encoder.

module parameterized_priority_encoder #(parameter INPUT_WIDTH=8,OUTPUT_WIDTH=3)
(
 input      [INPUT_WIDTH-1:0]  input_data,
 output reg [OUTPUT_WIDTH-1:0] output_data
);
 
integer                            ii;
 
always @* begin
  output_data = {OUTPUT_WIDTH{1'bx}};
  for(ii=0;ii<INPUT_WIDTH;ii=ii+1) if (input_data[ii]) output_data = ii;
end
 
endmodule  

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parameterized_priority_encoder.v368 bytes