Verilog serial in parallel out shift register
Submitted by abettino on Wed, 03/10/2010 - 20:06
The serial in parallel out shift register is another simple shift register, very similar to the serial in serial out shift register. The only difference being that entire contents of the shift register is the output. Please see Wikipeida for more discussion on the shift register and potential uses.
module serial_in_parallel_out #(parameter WIDTH=8) ( input clk, input data_in, output [WIDTH-1:0] data_out ); // register to hold shift values. reg [WIDTH-1:0] shift_reg; // sync process. always @(posedge clk) shift_reg <= {data_in,shift_reg[WIDTH-1:1]}; // data output of shift register. assign data_out = shift_reg; endmodule
| Attachment | Size |
|---|---|
| serial_in_parallel_out.v | 383 bytes |
verilog
can any one write the code for parallel-in serial-out shift register?
Thanku.
parallel-in serial-out shift register
module parallel_in_serial_out #(parameter WIDTH=8) (
input clk, ld
input [WIDTH-1:0] data_in,
output data_out
);
// register to hold shift values.
reg [WIDTH-1:0] shift_reg;
// sync process.
always @(posedge clk)
// For asynchronous load, use: always @(posedge clk or posedge ld)
if(ld)
shift_reg <= data_in;
else
shift_reg <= {shift_reg[WIDTH-1:1],shift_reg[0]};
// data output of shift register.
assign data_out = shift_reg[0];
endmodule
there is an error in that
there is an error in that code
shift_reg <= {shift_reg[WIDTH-1:1],shift_reg[0]};
that should be
shift_reg <= {shift_reg[0],shift_reg[WIDTH-1:1]};
Hello, The intention of the
Hello,
The intention of the code is to shift right so the way it is written in the snippet is correct. The code you have proposed will create linear feedback shift register where the LSB is fed back into the MSB.