Verilog Register

A register is a basic type in Verilog. It can be used to model both combinational and sequential logic. A verilog register must be assigned from within either an always or an initial block. The basic syntax is the reg keyword followed by the width of the signal and the name. Also see Verilog Flip Flops for the way to code flip flops in Verilog.

reg [7:0] example_reg;
 
always @* begin
  example_reg = foo;
end