Verilog Rising Edge Detector
Submitted by abettino on Sun, 03/21/2010 - 09:46
It is often necessary to detect when a particular signal is transitioning from low to high. It is also sometimes useful to get a pulse that is a single clock cycle wide to trigger other logic in the system. This snippet demonstrates how a single cycle wide pulse can be generated on the rising edge of a signal.
module rising_edge_detect ( input clk, input signal, output pulse ); reg signal_prev; always @(posedge clk) signal_prev <= signal; assign pulse = signal & ~signal_prev; endmodule
| Attachment | Size |
|---|---|
| rising_edge_detect.v | 191 bytes |
bug
This code will fail if the "signal"'s rising edge coincides with the "clk"'s rising edge.
This modules assumes that
This modules assumes that "signal" is properly synchronized into the "clk" domain. If this is the case it will have the proper setup time to ensure there is not a race condition. If you are dealing with an asynchronous input signal you will need to synchronize it to the "clk" domain before using this logic.
Interesting information about activation
I think this board is the proper place to ask you about the activation proccess. My link is not working properly, do you know why it is happening? http://www.hdlsnippets.com/?fa9644a52e1989d32059325c5f3,