Verilog Tristate Buffer for Bidirectional Signals

Often when connecting to an off chip component it is necessary to use a bidirectional signal for something like the data bus. This snippet demonstrates how this can be accomplished.

The output_enable signal is used to control whether or not the data_in_out signal is in high impedance. When output_enable is low, the bus is in high impedance and the rest of the logic can successfully read the value of data_in_out. When the output_enable signal is a high, the value from data_internal will go onto the bus. The signal data_internal can come from any other logic in the system and represents the value desired to go onto the bus at any time.

assign data_in_out = output_enable ? data_internal : 'bz;