VHDL CRC CRC16CCITT
Submitted by abettino on Wed, 03/31/2010 - 14:09
The CRC 16 CCITT is a very common and useful CRC algorithm. This snippets demonstrates how to implement this algorithm in VHDL. Also see the Verilog CRC16CCITT for additional discussion of this algorithm.
library ieee; use ieee.std_logic_1164.all; entity crc16ccitt is port ( clk : in std_logic; enable : in std_logic; reset_crc : in std_logic; data : in std_logic; crc : out std_logic_vector (15 downto 0) ); end crc16ccitt; architecture behavioral of crc16ccitt is signal crc_int : std_logic_vector (15 downto 0); signal xor12 : std_logic; signal xor0 : std_logic; signal xor5 : std_logic; signal xor16 : std_logic; begin xor16 <= crc_int(15) xor data; xor12 <= xor16 xor crc_int(11); xor5 <= xor16 xor crc_int(4); xor0 <= xor16 xor '0'; crc <= crc_int; process (clk) begin if (clk'event and clk='1') then if (reset_crc='1') then crc_int <= x"ffff"; else if (enable='1') then crc_int <= crc_int(14 downto 12) & xor12 & crc_int(10 downto 5) & xor5 & crc_int(3 downto 0) & xor0; end if; end if; end if; end process; end behavioral;
Online CRC generator tool
Even if CRC16 is common, the data width is not. Designs rarely use 1-bit data. It can be power of 2, or some other width for custom protocols.
There is an online CRC generator tool that generates Verilog/VHDL code for any data width: http://OutputLogic.com
math
1 IS a power of 2.
Serial data
While it is true that the internal data bus width is never 1 bit, it is very common to run a CRC on a serial bitstream. That is the intended use of this snippet.