VHDL Flip Flops

Submitted by abettino on Wed, 02/03/2010 - 08:09

This snippet demonstrates some basic flip flop styles in VHDL.

Rising edge triggered flip flop.

library ieee;
use ieee.std_logic_1164.all;
 
entity flip_flop_rising is
  port ( clk : in  std_logic;
         d   : in  std_logic;
         q   : out std_logic);
end flip_flop_rising;
 
architecture rtl of flip_flop_rising is
  begin
    process (clk)
    begin
      if (clk'event and clk='1') then
        q <= d;
      end if;
    end process;
  end rtl;

Falling edge triggered flip flop.

library ieee;
use ieee.std_logic_1164.all;
 
entity flip_flop_falling is
  port ( clk : in  std_logic;
         d   : in  std_logic;
         q   : out std_logic);
end flip_flop_falling;
 
architecture rtl of flip_flop_falling is
  begin
    process (clk)
    begin
      if (clk'event and clk='0') then
        q <= d;
      end if;
    end process;
  end rtl;

Rising edge triggered flip flop with active low asynchronous reset and clock enable.

library ieee;
use ieee.std_logic_1164.all;
 
entity async_reset_ce is
  port ( clk     : in  std_logic;
         n_reset : in  std_logic;
         ce      : in  std_logic;
         d       : in  std_logic;
         q       : out std_logic);
end async_reset_ce;
 
architecture rtl of async_reset_ce is
  begin
    process (clk,n_reset)
    begin
      if (n_reset='0') then
        q <= '0';
      elsif (clk'event and clk='1') then
        if (ce = '1') then
          q <= d;
        end if;
      end if;
    end process;
  end rtl;

Attachment	Size
flip_flops.vhd	1.23 KB

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Wrong edge?

Submitted by Anonymous on Wed, 09/15/2010 - 04:33.

Last FF is triggering on *falling* edge (not rising...)

Thanks, fixed that now.

Submitted by abettino on Wed, 09/22/2010 - 16:34.

Thanks, fixed that now.

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VHDL Flip Flops

Wrong edge?

Thanks, fixed that now.

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