VHDL Generate

library ieee;
use ieee.std_logic_1164.all;
 
entity generate_demo is
  port (
    clk      : in  std_logic;
    data_in  : in  std_logic_vector (7 downto 0);
    data_out : out std_logic_vector (7 downto 0)
    );
end generate_demo;
 
architecture behavioral of generate_demo is
  -- component to generate instances of.
  component flip_flop_rising is
  port (
    clk : in  std_logic;
    d   : in  std_logic;
    q   : out std_logic
    );
  end component;
 
begin
 
GENERATED_INSTANCES :
for k in 7 downto 0 generate
  flip_flop_rising_x : flip_flop_rising port map
    ( clk => clk,
      d => data_in(k),
      q => data_out(k) );
  end generate GENERATED_INSTANCES;
 
end behavioral;
 
library ieee;
use ieee.std_logic_1164.all;
 
entity flip_flop_rising is
  port ( clk : in  std_logic;
         d   : in  std_logic;
         q   : out std_logic);
end flip_flop_rising;
 
architecture rtl of flip_flop_rising is
  begin
    process (clk)
    begin
      if (clk'event and clk='1') then
        q <= d;
      end if;
    end process;
  end rtl;